Assessment of an FPGA Implementation of a Hybrid PUF Based on a Configurable Transient Effect Ring Oscillator and Ring Oscillator (TERORO-PUF)

Casado-Galán, A., Núñez, J., Tena-Sánchez, E., Potestad-Ordóñez, F. E., & Acosta, A. J., Assessment of an FPGA Implementation of a Hybrid PUF Based on a Configurable Transient Effect Ring Oscillator and Ring Oscillator (TERORO-PUF). Electronics, 15(3), 661, 2026.

https://doi.org/10.3390/electronics15030661

An FPGA-Based Event-Timing Front-End for Time-Resolved Sensing with Dual-Mode Experimental Characterization

Núñez, J., & Fiorelli, R., An FPGA-Based Event-Timing Front-End for Time-Resolved Sensing with Dual-Mode Experimental Characterization. Sensors, 26(10), 3268, 2026.

 https://doi.org/10.3390/s26103268

Simulated VO₂ Neuron With Embedded HfO₂ Memristive Synapse

Núñez, J., & Fiorelli, R., Simulated VO₂ Neuron With Embedded HfO₂ Memristive Synapse, in IEEE Electron Device Letters, vol. 47, no. 5, pp. 1025-1028, May 2026.

doi: 10.1109/LED.2026.3669601

A Fully Composable Hybrid Boolean Masked and Internal Fault Injection-Detecting AND Gate Gadget Proposal

Martín-González, M., Potestad-Ordóñez, F. E., Tena-Sánchez, E.  & Acosta, A. J., A Fully Composable Hybrid Boolean Masked and Internal Fault Injection-Detecting AND Gate Gadget Proposal. International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design (SMACD 2026), 2026.